It is common practice in the art of integrated circuit design to simulate the operation of a given circuit using a computer system. Using simulation software allows the circuit designer to verify the operation and margins of a circuit design before incurring the expense of actually building and testing the circuit. Simulation is particularly important in the semiconductor industry, where it is generally very expensive to design and produce a given integrated circuit. Through the use of such simulations, design errors or risks are hopefully identified early in the design process, and resolved prior to fabrication.
As data-rates approach and surpass multi-Gigabit/second (Gb/s) levels, the challenge of maintaining signal integrity across chip-to-chip interconnects grows due to the introduction of several analog phenomena which impact digital signals in the Gigahertz (GHz) frequency range. Fortunately, many of the parasitic effects of the inter-chip channel are not new and neither is the demand for speedy performance. Over the past century several communication media ranging from the telegraph to fiber optics have been explored and employed to meet the requirements of society. In every case bandwidth limitations have been overcome, or at least mitigated, through the ingenuity of communication engineers, and it is through the leveraging of proven signal conditioning techniques that data-rates have achieved their current levels.
Today the push toward ever higher operating speeds in electronics is driven, in part, by growing software complexity. Unfortunately, even as micro-processor unit (MPU) operating speeds and computational efficiency increase, the sheer complexity and mass of the associated software obscures much of the performance enhancement obtained at higher clock frequencies.
To maintain a given level of perceived performance, added complexity in the underlying simulation software must be balanced or tracked by improvements in processing efficiency. That processing efficiency is not only a function of the clock frequency of the MPU, but is also highly dependent upon the available system memory and the rate at which the MPU, memory, and other peripheral components communicate.
To accommodate the electronics consumer's insatiable appetite for bandwidth, MPUs are forced to share their computational burden with other application specific chips, for example, memory controllers or video processors. While on-chip signal distortion is typically reduced by parallelizing the data to allow for lower frequency intra-chip transmission, the growing cost of each input/output (I/O) pin on the integrated circuit package demands that the inter-chip data-rate be as high as possible, potentially resulting in severe signal degradation.
Obstacles facing digital communication engineers are not limited to the design of signal conditioning circuitry, but include the task of developing models and methodologies suitable for capturing and characterizing the newly encountered signal degradation as well as for analyzing and verifying proposed signal conditioning solutions.
The challenge associated with simulating channel-affected signals is highly correlated to the characteristics of the degradation. As will be discussed in greater detail, signals in any transmission medium experience both random and deterministic degradation. Random degradation, in the form of random Gaussian distributed voltage noise and timing noise or jitter stemming from thermal and shot noise, requires statistical quantification. Similarly, deterministic voltage noise and jitter are linked to several sources including power supply noise, inter-channel crosstalk, impedance discontinuities, component variance, and at high frequencies the response of the channel, resulting in a variety of observable characteristics, from periodicity to uncorrelated-bounded randomness. To model these noise components correctly requires the ability to designate their probability during the noise generation stage and consequently inject or superimpose these effects onto the underlying signal in a way reflecting what occurs in the actual system. The final success or robustness of a particular design is dependent, to a large measure, on the achieved realism of the simulation environment.
To date, industry standard simulators do not provide the level of noise and jitter generation control needed to accurately model a realistic communication link. While some of the more advanced, and hence expensive, tools provide for an accurate generation of Gaussian distributed noise and jitter, no simulator in existence allows for the derivation of signals exhibiting the random, periodic, and aperiodic jitter encountered in the real world. The nearest approximation is found in Agilent's Advanced Design System (ADS). ADS provides a square-wave clock with Gaussian distributed random jitter for transient simulation. In addition to serving as a jittery clock source, the clock function may also be used to trigger a random data source, thereby adding random jitter to the data signal. While the simulated jitter closely approximates a true Gaussian distribution, other jitter components commonly encountered in fabricated circuits are not directly realizable in ADS (sinusoidal jitter, uncorrelated bounded jitter, etc.).
To be fair, it is possible to formulate piecewise linear functions (PWLs) with tools like Matlab, as well as within Spice-based simulators, through the careful architecting of time and voltage vectors, wherein the voltage amplitude is designated for each step in time. But to approximate Gaussian distributed noise and jitter, as well as other specific noise distributions, over hundreds or thousands of cycles through this method is more than daunting.
Another challenge in simulating realistic signaling environments is tied to the underlying statistical assumption that sufficient samples of the behavior to be characterized are readily available. As such, it is becoming necessary to include more and more cycles with each simulation. At the same time, the relative size of each individual noise component is very small with respect to the overall cycle period, implying that fine voltage and timing resolution are also necessary. When fine simulated resolution is coupled with a greater number of simulated cycles, the result is an enormous amount of data and prohibitively lengthy simulation times. It is not uncommon for transistor-level transient (time-based) simulations to run for hours or even days. It is likewise not uncommon for such a simulation to fail due to a lack of memory resources.
Current Simulation Techniques:
At multi-Gb/s data rates, the statistical nature of signal degradation coupled with the already vanishing voltage and timing margins has lead to advances in channel and circuit modeling. Alternative computational algorithms have been incorporated into existing simulators to complement traditional circuit analysis, while and at the same time, high-level tools like Matlab are finding greater use in the verification process, as has been mentioned. To efficiently capture the true impact of the entire communication link on signal integrity with the requisite level of precision requires an interleaving of simulation at both the transistor and system levels.
Transistor-level analysis refers to the schematic entry of specific circuit blocks into Spice-like tools such as HSpice, PSpice, Cadence, and ADS for AC or transient analysis, which are complementary methods for determining signal integrity. AC analysis computes the frequency response of the channel or circuit and can help identify noise components and other degradation most visible in the frequency domain. Unfortunately, AC analysis is only carried out for a fixed circuit bias condition, while transient analysis provides a time-domain simulation of the circuit behavior accounting for dynamic changes in the circuit biasing resulting from varying input levels and/or supply noise, thereby presenting the real-time impact of environmental conditions on passing signals.
During transient analysis, differential equations relating the voltage and current at each circuit node are evaluated at specified points in time. The time that elapses with each computation increases when diodes, transistors, and other components exhibiting nonlinear voltage-to-current relationships are included. To control the overall simulation run time, the level of precision in both time and amplitude are often controllable. For example, the desired level of voltage or current resolution in Spice-based tools is designated through the AbsTol (absolute tolerance) parameter. Requiring tighter tolerance leads to a greater number of computational iterations to meet an associated error level while solving the differential nodal equations at each time step.
In a similar way, the timing resolution may be enhanced by decreasing the time span between each calculation. While simulators like HSpice, ADS, Spectre (Cadence), and HSim allow for the designation of a minimum transient step size, PSpice does not provide direct control over the minimum time step, but rather provides a maximum time step parameter which constrains the simulator to make at least one evaluation within the designated interval. Thus, for the purpose of jitter characterization, the timing precision of the industry-wide transient simulator is improved through a reduction in the simulated time step, the result of which is a simultaneous increase in both the simulation run time and the memory requirement.
In addition to the requirement of sub-picosecond timing resolution, the statistical nature of random noise and jitter demand that the signal-system interaction be computed over several clock cycles in order to provide the necessarily large number of samples required to properly build up probability distributions. Coupling the constraints of high resolution (small transient time step) with the need to observe the behavior over thousands or millions of cycles extends the transistor-level simulation run time and memory requirements even further.
An attempt to overcome the weaknesses of the general transient simulator has lead to the development of alternative time-domain algorithms including Harmonic Balance, Circuit Envelope, and Periodic Steady State simulation. While these techniques have many distinct features, they all seek to avoid or minimize the time step dependency of transient simulation by operating as much as possible in the frequency domain. See Agilent Technologies Technical Staff, “Guide to Harmonic Balance Simulation m ADS,” Available online at http://eesof.tm.agilent.com/docs/adsdoc2004A/pdf/adshbapp.pdf, (September 2004); J. Sifri et. al., “RF Design Environment closes verification gap”, in Microwaves & RF for Designers at Higher Frequencies, available online: http://www.mwrf.com/Articles/Index.cfm?ArticleID=6854 (November 2003); and R. Telichevesky et al., “Receiver Characterization Using Periodic Small-Signal Analysis,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 449-452 (May 1996), all of which are submitted with an Information Disclosure Statement filed with this application and are incorporated by reference herein in their entireties.
As long as the circuit element passing the signal can be accurately modeled as a linear time-invariant (LTI) system, the time-consuming process of convolving the signal with the circuit impulse response in the time-domain may be replaced by simple vector multiplication in the frequency domain due to the relationship:A{circle around (x)}B=FT{A}xFT{B}where {circle around (x)} denotes convolution and FT{ } denotes the Fourier Transform. The computational efficiency gained through this substitution is illustrated by considering the time-domain convolution of two vectors A and B, which could represent a signal and the impulse response of the circuit through which it is passing. Recall first that the process of discrete-time convolution is carried out through the formula:
      C    ⁡          (      n      )        =            ∑              k        =                  -          ∞                    ∞        ⁢                  ⁢                  A        ⁡                  (          k          )                    ⁢              B        ⁡                  (                      n            -            k                    )                    
Due to the finite length of the vectors under consideration, the sum need not be carried out to infinity. Thus, the number of computational steps to perform the convolution is found through
      1    +    M    +    N    +          2      ⁢                        ∑                      k            =            0                    N                ⁢                                  ⁢                              (                          M              +              N              -              k                        )                    2                      -          α      ⁢                          ⁢              M        2              where      α    =          {                                    1                                                              if                ⁢                                                                  ⁢                M                            +                              N                ⁢                                                                  ⁢                is                ⁢                                                                  ⁢                even                                                                          0                                                              if                ⁢                                                                  ⁢                M                            +                              N                ⁢                                                                  ⁢                is                ⁢                                                                  ⁢                odd                                                        where M and N are the number of elements in the longer and shorter of the two arrays respectively. Accordingly, the convolution of two vectors of 1000 elements each would require 4,670,669,001 mathematical steps. This may be contrasted with the number of steps needed to convert the two vectors to the frequency domain, perform an element-to-element multiplication, and return to the time domain, a process often referred to as Fast Convolution. When the Fourier Transform and Inverse Fourier Transform processes are carried out via the Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) algorithms, the time-to-frequency and frequency-to-time domain translations require as little as (½)×(N log2N) complex multiplications and N log2N complex addition steps each. See M. H. Hayes, “Statistical Digital Signal Processing and Modeling,” 1st ed. New York: John Wiley & Sons, Inc., pp. 20 (1996). For the two equal length vectors under consideration, this leads to a total number of 4.5N log2N+N, or 45,846 computational steps to convert both vectors to the frequency domain, multiply them and return to the time domain. To be fair, increased accuracy and efficiency in the FFT algorithm is insured by padding each data set with zeros to the nearest power of two greater than the sum of the two data set lengths. Thus for M=N=1000, the actual number of data points involved in the FFT process will equal 2048, causing the total number of steps in the overall calculation to increase to 103,424, yet still significantly shorter than direct convolution.
Unfortunately, this reduction in mathematical steps is only realized when the simulated circuits can be linearized. Thus Harmonic Balance and the other more sophisticated simulation algorithms tend to divide the simulated system down into those parts which can be appropriately modeled as LTI, and those parts which require nonlinear analysis (e.g. circuits containing diodes and transistors passing large signals). In Circuit Envelope simulation, further efficiency is gained by only performing frequency domain multiplication over the spectrum of the passing signal while avoiding unnecessary calculations at unrelated frequencies. The ability of these more sophisticated algorithms to handle nonlinear circuit elements while exploiting the speed of frequency domain calculation is somewhat washed out, as they tend to target radio frequency (RF) circuit design, and in doing so incorporate functionality (complexity), such as signal mixing and inter-modulation analysis, not typically considered or even applicable in baseband link verification.
Because simulation time and memory requirements associated with transistor level Spice-based evaluation are prohibitive, much of high-speed link design and verification is carried out at the system level with programs like Matlab. These tools allow the designer to take a more statistical look at the link behavior. See B. K. Casper et al., “An Accurate and Efficient Analysis Method for Multi-Gb/s Chip-to-Chip Signaling Schemes,” in Digest of Technical Papers from the IEEE Symposium on VLSI Circuits, pp. 54-57 (June 2002), which is incorporated herein by reference in its entirety.
Modeling Trends:
To speed design-to-market time, the growing trend is to compartmentalize system circuitry during the verification process. Rather than simulate the full system at the transistor level, smaller circuit blocks are characterized in Spice-based simulators at the transistor level, and then those characteristics are used to construct behavioral models that may be included in simulations at higher levels of abstraction in programs like Matlab. This methodology is very effective when implemented carefully, but has the potential for providing unrealistic performance predictions, as much of the nonlinear circuit behaviors are lost in the translation from transistor level to behavioral circuits.
In addition to breaking the system down into more manageable blocks, it is not uncommon for voltage and timing noise to be evaluated independently. One of the weaknesses in this approach is that it fails to capture the interaction and interdependency of voltage noise and timing jitter, which deficiency may be linked to an inability to generate waveforms with control over both components of signal degradation. As will be shown, voltage and timing noise exhibit a synergistic relationship, wherein each leads to the other and together they combine to limit performance wherever they are encountered.
At the lower data-rates of the past, voltage noise was the dominant concern, leading to signal-to-noise ratio (SNR) boosting circuits like the matched filter and inter-symbol interference (ISI) canceling channel equalizers. See, e.g., R. W. Lucky et al., “Automatic Equalization for Digital Communication,” Proceedings of the IEEE (Correspondence), vol. 53, pp. 96-97 (January 1965); M. E. Austin, “Decision-Feedback Equalization for Digital Communication Over Dispersive Channels,” Massachusetts Institute of Technology: Research Laboratory of Electronics, Tech. Rep. 461 (August 1967); and J. W. M. Bergmans, “Decision Feedback Equalization for Digital Magnetic Recording Systems,” IEEE Transactions on Magnetics, vol. 24, no. 1, pp. 683-688 (January 1988), all of which are incorporated herein by reference in their entireties. But at multi-Gb/s data-rates, the inherently short symbol period or unit interval (UI) has shifted attention from the voltage axis to the time axis. And whereas noise budgets were once an essential part of the initial design specification, jitter budgets are now the more common focus. While this trend may appear to justify the independent analysis of voltage noise and jitter when one of the two is the more dominant performance limiter, increased accuracy is still achieved when both noise components are considered simultaneously.
The growing emphasis on timing has given way to new terminology, closely resembling the vocabulary already associated with voltage domain characteristics (jitter impulse response, jitter transfer function, etc.). With the jitter transfer function, and its time-domain corollary the jitter impulse response, it is possible to track the effects of a system on passing jitter, in much the same way that the effects of a system on signal amplitude are computed through the voltage transfer function. Thus, the jitter accumulation that occurs as a signal passes through a particular system block may be calculated through the convolution of the jitter distribution at the block input with the block's jitter impulse response. Similarly, just as uncorrelated noise may be directly added to a signal passing a certain point in the system, when modeled independent of any signal, uncorrelated jitter may be directly added to the accumulated jitter at any point as well.
In real systems, however, voltage noise at a particular point may lead to timing noise in various ways depending upon how the two are coupled, and the accuracy of independent jitter modeling would be improved by approximating that coupling or correlation between voltage and timing. For example, and as shown in FIG. 1, it is well understood that voltage noise in a signal is translated into timing noise at each signal transition through the signal slew-rate. Thus, FIG. 1 shows the same voltage noise distribution translated into two distinct jitter distributions through fast and slow rising edges. As the voltage noise causes fluctuations in the signal at each point in time, the time at which the signal crosses the detection threshold will also vary resulting in a corresponding change in the observed jitter. For Gaussian distributed noise, the rms value of the voltage distribution may be divided by the slope of the signal transition near the midway point to approximate the rms jitter level, verifying the well known fact that faster edges, though potentially problematic for other reasons, often result in lower observed jitter.
A second connection between voltage and timing noise is through the power supply. When a transistor's supply levels vary, through voltage droop or ground bounce, at least two things happen. The first is that those perturbations may bleed through to the output signal via parasitic capacitances, depending upon the slope of the perturbations' edges or the frequency of on-going supply noise. Second, slower supply variations change the bias conditions of the circuit devices and may speed up or slow down the device performance for a moment leading to timing deviation in any corresponding output transitions. In the case of a CMOS inverter, slower perturbations may alter the voltage trip point, again shifting the output transition in time. Additional coupling of supply noise to the signal may also occur through the several pull-up and pull-down resistors scattered throughout the system.
To account for the points just discussed, more careful models adopt a voltage noise to jitter scaling factor, which approximates the average ΔTedge/ΔVsupply. While such approximations do provide useful jitter predictions, when designing to meet a required jitter budget they fail to capture much of the nonlinear voltage-to-noise translation that occurs in realized circuits, as most of these approaches make assumptions regarding the biasing and general performance of the associated transmit and receive circuitry. These methods also fail to capture the sensitivity of the data sampling mechanism to noise, and to account for the combined degradation imposed by simultaneous voltage and timing noise.
In addition, not all jitter exhibits such a deterministic relationship with voltage noise. For example, the magnitude of an oscillator's phase noise may depend upon voltage noise in the silicon substrate, yet the relationship is unpredictable. Similarly, the jitter at the output of a phase-locked loop (PLL) is related to the jitter of the input signal filtered by the control loop plus the contribution of power supply noise nonlinearly translated into timing noise through several distinct circuit components. In this case, knowledge of the environmental noise is not enough to accurately predict the jitter at the PLL output, and this difficulty in correlating voltage and timing noise sometimes makes it necessary to add jitter terms directly to the model equations. This turns out to be difficult, and as a result, a new model is often adopted which neglects the voltage dimension of the signal when jitter is the dominant concern.
Perhaps the strongest argument for developing full signals with noise and jitter, rather than maintaining independent noise and jitter models, is the impact of ISI. While unbounded Gaussian noise and jitter lead to long term bit errors, depending upon the bandwidth of the channel, ISI and the corresponding data-dependent jitter (DDJ) may dominate the short term signal degradation. Recent papers have proposed methods for predicting the DDJ distribution from the relationship of the data-rate and the channel bandwidth, see J. Buckwalter et al., “Predicting Data-Dependent Jitter,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, no. 9, pp. 453-457 (September 2004), which is incorporate herein by reference in its entirety, but these techniques still do not provide a means for visualizing the interaction of a dynamic or moving sampling point with a moving data eye.
Still other methods exist for measuring signal integrity while avoiding full signal generation, including the construction of worst-case eye diagrams through peak distortion analysis and the formulation of bit error rate (BER) eye diagrams through statistical analysis, as presented in the B. K. Casper reference cited earlier. Worst case eyes are useful for predicting performance limits, but as chip-to-chip links often target BERs of 10−12, a worst case eye approximating 10−20 is overkill and may lead to unnecessary pessimism and un-required compensation in the design. The BER eye is more informative in that it identifies the BER associated with a given skew in the detection reference voltage and/or the sample timing. Unfortunately, these last few techniques are based on the system impulse response, which again corresponds to a specific circuit and system condition (temperature, biasing, etc.).
With the following background in hand, it should be apparent that the art of signal simulation includes several different techniques, each with their advantages and disadvantages. However, an improved solution would tend to promote the advantages without concomitant disadvantages. In other words, an improved signal simulation technique would at least: allow for the formation a signal for simulation in which noise, such as timing jitter, is easily and realistically modeled; allow the inter-relationship between voltage noise and timing jitter to be respected and concurrently modeled; allow for the simulation of both period and aperiodic signals; allow for the simulation of linear or nonlinear signals; and with good computational efficiency across all such types of signals. The disclosed techniques achieve such results in a manner easily implemented in a typical computerized system or other computerized circuit simulation software package.